Vacant job

Key Responsibilities

The candidate will be responsible for verifying advanced controller and peripheral IPs including PCIe, DDR/LPDDR, CXL, Ethernet, UAL Controllers, and AMBA peripherals. The role demands hands-on verification experience, autonomous debugging capability, and the ability to develop robust verification environments and test cases from scratch.

Develop and maintain UVM/SystemVerilog-based verification environments for complex controller and peripheral IPs.

Perform verification activities for PCIe Controllers (including PCIe Gen7), DDR/LPDDR Controllers, CXL interfaces, High-Speed Ethernet, UAL Controllers, and AMBA peripherals.

Design, implement, and execute comprehensive test plans and verification strategies.

Create new test cases, sequences, assertions, and coverage models from scratch to ensure functional correctness and protocol compliance.

Utilize industry-standard protocol VIPs for efficient verification and protocol validation. Debug simulation failures independently and perform root-cause analysis for complex issues.

Analyze coverage metrics and improve verification quality to achieve coverage closure.

Support regression runs, issue tracking, and continuous improvement of verification methodologies.

Technical Skills & Tools

• Strong expertise in UVM (Universal Verification Methodology) and SystemVerilog.

Hands-on experience with complex HPC protocols such as:

• PCIe (including Gen7)
• CXL
• DDR / LPDDR
• High-Speed Ethernet
• AMBA Protocols

Experience in protocol VIP integration and usage.

• Strong debugging and problem-solving skills in simulation and verification environments.
• Knowledge of coverage-driven verification methodologies.
• Ability to work independently while contributing effectively within a collaborative team environment.
• Protocol VIPs for PCIe, DDR/LPDDR, Ethernet, and related interfaces.
• Simulation, debugging, and regression management tools within ASIC/SoC verification environments.

Preferred Experience

Experience in verification of high-performance ASIC/SoC designs.

Prior exposure to controller and subsystem-level verification.

Strong understanding of verification architecture and reusable testbench development.

Experience working in fast-paced semiconductor or HPC design environments.

Ability to independently drive verification tasks from planning through closure.

Application Method: Interested candidates can apply by sending their profile to [email protected]