Vacant job

Xenergic is a high-tech semiconductor company providing cutting-edge, high-speed, low-power embedded memory IP solutions in advanced technology nodes. Our memory solutions are targeted at market segments ranging from IoT and mobile applications to high-end servers and AI accelerators.

Who we are looking for

We are looking for a passionate, highly motivated, and talented test and verification engineer to perform tests, measurements, and functional verification required for the validation of our memory solutions.

Key Responsibilities

The key responsibilities in this position include:

• Simulating and verifying designs at the pre-production level
• Generating and validating required test patterns for post-silicon measurements
• Designing custom PCBs for measurement and setting up the measurement environment
• Carrying out post-silicon measurements
• Documentation

In this position, you will interact with highly skilled designers in both analog and digital domains and plan test and verification scenarios in both pre- and post-silicon stages. You will contribute to pre-silicon verification by testing memory models and different design sections after receiving specifications from the digital and analog teams. In the post-silicon stage, you will prepare various test scenarios and perform the required tests. Documentation and regular discussion with the design team will also be an important part of the work.

The following are mandatory requirements:

• Master's degree or higher in electrical engineering or related fields
• General understanding of integrated circuits and memory design
• Skilled in working with electronics test instruments such as logic analyzers, pattern generators, oscilloscopes, signal sources, and other related debug and analysis devices
• Strong scripting skills in Python for test automation and data processing
• Good experience with PCB design, component selection, and soldering of SMD components
• Knowledge of Verilog/SystemVerilog and standard RTL simulators
• Fluent in English, both in writing and speaking
• Good communication skills and ability to work in a team

The following competencies are not mandatory but would be beneficial:

• Prior work experience as a post-silicon validation engineer
• Basic knowledge of CAD tools and the ability to interact with analog teams
• EMIR-aware layout design concepts
• Understanding of the impact of layout on post-layout parasitic extraction
• Very good understanding of memory architecture and DFT interfaces
• Skilled in working with automation using Python, TCL, and Makefiles
• Knowledge of circuit-level simulators and equivalence checking between models and circuits
• Experience in schematic and layout design

Do you have what we are looking for? We want to hear from you! Send your application (CV and cover letter) via e-mail to [email protected]