Vacant job

Veritaz is a leading IT staffing solutions provider in Sweden, committed to advancing individual careers and aiding employers in securing the perfect talent fit. With a proven track record of successful partnerships with top companies, we have rapidly grown our presence in the USA, Europe, and Sweden as a dependable and trusted resource within the IT industry.

Assignment Description:

We are looking for a Senior ASIC Designer to join our dynamic team.

What you will work on:

• Participate in the development of complex ASIC and large FPGA designs.
• Work on projects involving multi-clock domains and parameterized IP block design.
• Utilize System Verilog for ASIC development and contribute to SOC/DSP architecture design.
• Engage in tasks related to packet-based communication protocols.
• Collaborate effectively in teams to achieve project goals and meet customer requirements.

What you bring:

• Over 5 years of experience in ASIC development, with a strong foundation in complex ASIC and/or large FPGA design.
• Expertise in multi-clock domains and parameterized IP block design.
• Proficiency in System Verilog and familiarity with SOC/DSP architecture.
• Experience with packet-based communication protocols.
• Strong English skills, both written and spoken.

Preferred qualifications:

• Experience in systemization and architecture design.
• Background in backend tasks, including timing constraints, timing optimization, and formal verification.
• Knowledge of UVM verification and simulation tools like Xcelium.
• Proficiency with version control systems (e.g., GIT) and linting tools (e.g., Spyglass).
• Scripting skills in Python, shell scripting, or Tcl.
• Experience in the telecom sector.